1. Technical Field of the Invention
This invention relates generally to general-purpose integrated circuits and more particularly to programmable logic devices.
2. Description of Related Art
Programmable devices are a class of general-purpose integrated circuits that can be configured for a wide variety of applications. Such programmable devices have two basic versions, mask programmable devices, which are programmed only by a manufacturer, and field programmable devices, which are programmable by the end-user. In addition, programmable devices can be further categorized as programmable memory devices or programmable logic devices. Programmable memory devices include programmable ready-only memory (PROM), erasable programmable read-only memory (EPROM) and electronically erasable programmable read-only memory (EEPROM). Programmable logic devices include programmable logic array (PLA) devices, programmable array logic (PAL) devices, erasable programmable logic devices (EPLD), and programmable gate arrays (PGA).
Field programmable gate arrays (FPGA) have become very popular for telecommunication applications, Internet applications, switching applications, routing applications, et cetera. Generally, an FPGA includes a programmable logic fabric and a programmable input/output section. The programmable logic fabric may be programmed to perform a wide variety of functions corresponding to the particular end-user applications. The programmable logic fabric may be implemented in a variety of ways. For example, the programmable logic fabric may be implemented in a systematic array configuration, a row base configuration, a sea-of-gates configuration, or a hierarchical programmable logic device configuration.
The programmable input/output section is fabricated on the perimeter of a substrate supporting the FPGA and provides coupling to the pins of the integrated circuit package allowing users access to the programmable logic fabric. Typically, the programmable input/output section includes a number of serial/deserial transceivers to provide access to the programmable logic fabric. Such transceivers include a receiver section that receives incoming serial data and converts it into parallel data and a transmitter section that converts outgoing parallel data into an outgoing serial data stream.
Since FPGA's are used in a wide variety of applications, which are typically governed by one or more standards; the transceivers are programmed, to some degree, to support the appropriate standard. As such, the receiver section is programmed to convert serial data into parallel data and the transmitter section is programmed to convert parallel data into serial data in accordance with the same standard. This, however, provides a limitation in the use of an FPGA in that the transmit path and receive path must be coupled to the same device, or devices that conform to the same standard. Thus, using today's FPGA, if an application requires the FPGA to receive data from one device in accordance with a 1st standard and transmit process data to another device in accordance with a 2nd standard, the FPGA would have to dedicate 2 transceivers: 1 for the receiving of data and the other for the transmitting of data. In this example, the transmitter section of the 1st transceiver is always idle and the receiver section of the 2nd transceiver is always idle. In the heavily competitive integrated circuit market, having die area consumed by unused circuitry is extremely costly.
In addition, the transceivers of an FPGA are programmed in accordance with a particular standard being supported by the FPGA. As such, each of the transceivers is programmed to support the same standard. As such, the devices to which the FPGA is coupled must also conform to the same standard. As such, the flexibility of usage of an FPGA is limited by requiring the environment in which it resides to utilize the same standard.
Further, the transceivers of the I/O section use a different clock domain than the programmable logic fabric. As the speed of the incoming and outgoing serial data increases well into the gigabit-per-second range, the separate clock domains of the input/output section and the programmable logic fabric are presenting synchronization issues between the two sections, resulting in corruption of data.
Therefore, a need exists for a universally programmable FPGA that provides universally programmable transceivers and further provides universal synchronization.